Dr. Srinivas Boppu Assistant Professor
School of Electrical and Computer Sciences
( Department of Electronics & Communication Engineering)

Research Interests

High Level Synthesis, Programmable Hardware Accelerators, Coarse-Grained Reconfigurable Architectures, System-on-Chip Design, Low power VLSI, and CAD for VLSI.

Contact Details

  • Room No: 106, School of Electrical Sciences.
  • 06747135752
  • srinivas@iitbbs.ac.in

Other Profile Link(s)


 Degree Discipline Year School
  Ph.D. Hardware-Software-Co-Design 2015 University of Erlangen-Nuremberg, Germany.
  M.Sc. IC Design 2009 NTU Singapore, Singapore, TU Munich, Germany.





Recent Publications (International Journals)

1S. Boppu, F. Hannig and J. Teich. Compact Code Generation for Tightly-Coupled Processor Arrays. Journal of Signal Processing Systems, 77(1-2):5-29, 2014.
2 F. Hannig, V. Lari, S. Boppu, A. Tanase and O. Reiche. Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Transactions on Embedded Computing Systems (TECS), 2014.
3E. Glocker, S. Boppu, Q. Chen, U. Schlichtmann, J. Teich and D. Schmitt-Landsiedel. Temperature modeling and emulation of an ASIC temperature monitor system for Tightly-Coupled Processor Arrays (TCPAs) on FPGA. In Journal of Advances in Radio Science,Vol. 12, pages 103–109, 2014.
4V. Lari, S. Muddasani, S. Boppu, F. Hannig, M. Schmid and J. Teich. Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 18, No. 1, Article 2, Pages 2:1–2:25, January 2013.

Conferences (International)

1J. Teich, S. Boppu, F. Hannig and V. Lari. Compact Code Generation and Throughput Optimization for Coarse-Grained Reconfigurable Arrays. In Transforming Reconfigurable Systems: A Festschrift Celebrating the 60th Birthday of Prof. Peter Cheung, Editors W. Luk, and George A. Constantinides, Chapter 10, pp.167--206, Imperial College Press, London, UK, April 2015.
2M. Blocherer, S. Boppu, V. Lari, F. Hannig and J. Teich. Transactor-based debugging of massively parallel processor array architectures. 1st International Workshop on Multicore Application Debugging (MAD), Garching, Germany, November 14-15, 2013.
3S. Boppu, F. Hannig and J. Teich. Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators. Proceedings of the 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 10–17. IEEE, Washington, D.C., USA, Jun. 5-7, 2013.
4V. Lari, S. Boppu, F. Hannig, J. Teich and T. Scott. Hybrid Prototyping of Tightly-Coupled Processor Arrays for MPSoC Designs. Designer Track Poster Presentation at the 50th Design Automation Conference (DAC 2013), Austin, TX, USA, Jun. 2-6, 2013.
5F. Hannig, M. Schmid, V. Lari, S. Boppu and J. Teich. System Integration of Tightly-Coupled Processor Arrays using Reconfigurable Buffer Structures. Proceedings of the ACM International Conference on Computing Frontiers (CF), Ischia, Italy, May 14-16, 2013.
6 V. Lari, S. Boppu, F. Hannig, S. Muddasani, B. Kuzmin and J. Teich. Resource-Aware Video Processing on Tightly-Coupled Processor Arrays. Hardware and Software Demo, University Booth at Design, Automation and Test in Europe (DATE), Grenoble, France, Mar. 18-22, 2013.
7S. Muddasani, S. Boppu, F. Hannig, B. Kuzmin, V. Lari and J. Teich. A Prototype of an Invasive Tightly-Coupled Processor Array. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), pp. 393-394, Karlsruhe, Germany, October 23-25, 2012.
8V. Lari, S. Muddasani, S. Boppu, F. Hannig and J. Teich. Design of Low Power On-Chip Processor Arrays. In Proceedings of the 23rd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pp. 165-168, Delft, Netherland, Jul. 9-11, 2012.
9S. Boppu, F. Hannig, J. Teich and R. Perez-Andrade. Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp. 392-397, Cancun, Mexico, Nov. 30 - Dec.2, 2011.
10V. Lari, S. Boppu, S. Muddasani, F. Hannig and J. Teich. Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays. International Workshop on Adaptive Power Management with Machine Intelligence at International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov. 10, 2011.

Academic Honors & Awards

  • Received full scholarship for pursuing Masters in IC Design---jointly offered by Nanyang Technological University, Singapore and Technical University of Munich, Germany.

Research Scholar

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